1. Field of the Invention
The present invention relates to an input buffer, which fetches and latches an input signal in synchronization with a clock, and more particularly to an integrated circuit device having an input buffer capable of operating in correspondence with a highspeed clock.
2. Description of the Related Art
To achieve highspeed operation, an integrated circuit device like a highspeed synchronous DRAM has input buffers, which, in synchronization with a clock from the control side, receive and latch inputted signals, such as data, address, and control signals, supplied in synchronization with this clock. Such input buffers receive and internally latch the supplied input signals in synchronization with the rising edge of a clock supplied as a strobe signal. Therefore, the controller side can provide an input signal in synchronization with a clock, enabling the realization of highspeed operation without need for concern over problems such as propagation delay time within the circuit substrate on which the integrated circuit device is mounted.
FIG. 12 is a block diagram of input buffer elements of a conventional integrated circuit device. An integrated circuit device 1 has a clock buffer 10, which receives a clock CLK, a clock compensating element 12, which compensates the phase of an internal clock iclk outputted from the clock buffer 10, and input buffers 20, 21, 22, which, in synchronization with an internal clock clk outputted by the clock compensating element, receive an externally-supplied address Add, control signal .phi..sub.CON, and data signal DQ.
FIG. 13 is a timing chart showing the operation of the input buffer of FIG. 12. As shown in FIG. 13, the input buffers 20, 21, 22 receive and internally latch supplied input signals Add, .phi..sub.CON, DQ in synchronization with the rising edge of an internal clock clk phase synchronized to an external clock CLK.
However, if, for example, the frequency of the synchronization clock CLK is around 200 MHz, an input buffer can reliably receive an input signal in synchronization with the rising edge of that clock CLK, but if, for example, the frequency of the synchronization clock CLK is a high frequency of 400 MHz, the operating speed of a input buffer reaches its limit, making a normal input signal capture operation impossible. Moreover, with a highspeed synchronization clock, there are cases in which the clock waveform is disturbed by such factors as noise, making the pulse width extremely narrow, with the result that an input buffer cannot reliably receive an input signal.
Accordingly, an object of the present invention is to provide an integrated circuit device having an input buffer capable of reliably capturing a supplied input signal in synchronization with a highspeed clock.
Furthermore, another object of the present invention is to provide an integrated circuit device having an input buffer capable of reliably receiving a supplied input signal in synchronization with a clock of a wide range from low speed to high speed.